As is known in the art, a processor includes a variety of sub-modules, each adapted to carry out specific tasks. In one known processor, these sub-modules include the following: an instruction cache, an instruction fetch unit for fetching appropriate instructions from the instruction cache; decode logic that decodes the instruction into a final or intermediate format, microoperation logic that converts intermediate instructions into a final format for execution; and an execution unit that executes final format instructions (either from the decode logic in some examples or from the microoperation logic in others).
Under operation of a clock, the execution unit of the processor system executes successive instructions that are presented to it. As is known in the art, an instruction may be provided to the execution unit which results in no significant task performance for the processor system. For example, in the Intel® X86 processor systems, a NOP (No Operation) instruction causes the execution unit to take no action for an “instruction cycle.” An instruction cycle as used herein is a set number of processor clock cycles that are needed for the processor to execute an instruction. In effect, the NOP instruction stalls the processor for one instruction cycle.
A limitation of the NOP instruction is that it stalls the processor for a set unit of time. Thus, using one or more NOP instructions, the processor can only be stalled for an amount of time equal to a whole number multiple of instruction cycles.
Another limitation of the NOP instruction is that the execution unit of the processor is unable to perform any other instruction execution. For example, instructions to be executed by the execution unit may be divided into two or more “threads.” Each thread is a set of instructions to achieve a given task. Thus, if one of the threads includes a NOP instruction, this instruction is executed by the execution unit and stalls the entire processor (i.e., execution of the other thread cannot be done during the execution of the NOP instruction).
In view of the above, there is a need for an improved method and apparatus for pausing processor execution that avoids these limitations.